For saving the layout space or increasing the interconnection efficacy, at least two integrated circuits (ICs) may be stacked as a single IC package. That is, a three-dimensional (3D) stack packaging technology is used to package the integrated circuits. For implementing the 3D stack packaging technology, through-silicon vias (TSVs) are widely used. The through-silicon via is a vertical electrical connection technology via completely passing through a silicon wafer or die. Nowadays, a 3D integrated circuit (3D IC) is mainly applied to many fields such as memory stacks, image sensors or the like.
For implementing a TSV interconnect technology, a trench is firstly created in a wafer by an etching process or a laser-drilling process, and then a conductive material (e.g. copper, polysilicon, tungsten, or the like) is filled into the trench to form an interconnect between two stacked chips. The wafer is thinned, and then stacked and bonded with another wafer. Since the through-silicon via permits vertical electrical connection between stacked wafers, the use of the through-silicon via can largely minimize the size of the chip package, enhance the chip and reduce the chip power loss.
Depending on the point in the semiconductor process flow, the TSV forming method may be classified into three types, i.e. a via-first through-silicon via (via-first TSV) method, a via-middle through-silicon via (via-mid TSV) method and a via-last through-silicon via (via-last TSV) method. The TSV formed at front-end-of-line (FEOL) stage is referred as the via-first TSV. The TSV formed at back-end-of-line (BEOL) stage is referred as the via-mid TSV. The TSV formed by the via-last method is referred as the via-last TSV.
The via-first TSV is formed in the blank wafer prior to any CMOS process by a deep reactive-ion etching (DRIE) process. Since the subsequent CMOS manufacturing steps have to withstand thermal processes, usually at higher than 1000° C., the mostly used filling material is polysilicon. Moreover, the conductive material filled in the via-mid TSV is copper (Cu) or tungsten (W). Whereas, the via-last TSV is formed in a predetermined blank region of the wafer after the CMOS device is produced.
For forming the via-first TSV or the via-mid TSV, since the whole CMOS process is not completed, high temperature treating and annealing processes should be done after the step of drilling the via and the step of filling the conductive material. Due to these processes, the conductive material filled in the via-first TSV or the via-mid TSV will be thermally expanded.
For example, a copper layer is used as a filling material of the via-mid TSV. Even if the copper layer is evenly filled in the via, the subsequent high temperature treating and annealing processes may result in extrusion or degradation of the electroplated copper because the large thermal expansion coefficient difference between the copper and the silicon may cause thermo-mechanical stress. The structure of the wafer is adversely affected by the thermo-mechanical stress.
FIG. 1A schematically illustrates a through-silicon via forming method according to the prior art. For example, the substrate 10 is a silicon substrate with a contact etch stop layer (CESL) and an interlayer dielectric layer (ILD) (not shown). A dielectric layer 11, a seed layer 13 and a through-silicon via conductor 12 and are sequentially formed within a trench of the substrate 10. The through-silicon via conductor 12 is made of a conductive material (e.g. copper). The seed layer 13 is arranged between the through-silicon via conductor 12 and the dielectric layer 11 for providing good crystal growth orientation of film coating. The use of the dielectric layer 11 may facilitate isolating copper from silicon and prevent diffusion of copper into silicon.
Please refer to FIG. 1A again. After a chemical mechanical polishing (CMP) process is performed, the surfaces of the dielectric layer 11 and the through-silicon via conductor 12 are flattened, so that the surface of the through-silicon via conductor 12 is at the same level as the surface of the substrate 10. Consequently, the through-silicon via conductor 12 can be used in the subsequent wiring process.
However, during the subsequent process of forming a dielectric isolation layer 16 and a metal layer 15, the high temperature treating process may result in extrusion of the through-silicon via conductor 12. Due to the extrusion of the through-silicon via conductor 12, as shown in FIG. 1B, the through-silicon via conductor 12 is protruded from the surface of the substrate 10.
As described in FIGS. 1A and 1B, the conventional methods of forming the via-first TSV or the via-mid TSV have some drawbacks. For example, after the through-silicon via conductor is filled in the trench and the surface of the through-silicon via conductor is flattened to be at the same level as the surface of the substrate, the subsequent high temperature treating and annealing processes may result in extrusion of the through-silicon via conductor because of volume expansion. Due to the volume expansion of the through-silicon via conductor, the through-silicon via conductor will be protruded from the surface of the substrate to extrude the overlying semiconductor circuit. Under this circumstance, the stack structure is possibly damaged. Therefore, there is a need of providing an improved through-silicon via method.